1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular to a semiconductor memory device driven by two power supply potentials supplied independently from each other and a reference potential.
2. Description of the Background Art
A semiconductor memory device such as a dynamic random access memory (hereinafter referred to as DRAM), which utilizes a minor potential difference by amplifying it, includes a voltage down converter for generating a power supply voltage for an array to achieve a stable operation. For saving the power consumption, peripheral circuitry is driven by a dedicated power supply voltage which is directly connected to an external source. In the conventional DRAM, a read column select line and a write column select line are driven by a power supply voltage, either the power supply voltage for the array or the power supply voltage for the peripheral circuitry.
Along with the miniaturization of the semiconductor integrated circuit according to the scaling law, the power supply voltage has been decreased. Hence, the fluctuation of drivability of the transistor caused by the fluctuation of gate length and threshold voltage in the manufacturing process has become apparent, and the fluctuation in operating voltage causes a significant change in the switching characteristics and the operation speed of the circuit of the transistor. The power supply voltage for the array and the power supply voltage for the peripheral circuitry, though with the same standard value, vary according to the voltage drop and disturbance during the operation.
To solve the problems as described above, it has been proposed that the select level of a column select signal supplied to the gate of an MOS transistor, which connects a bit line and a data line, be set to a voltage according to a variation of a power supply voltage supplied from an external terminal at the low voltage side in the normal operation range, and be set to a voltage according to a variation of a down-converted voltage at the high voltage side in the normal operation range, to achieve a stable high-speed operation (for example, see Japanese Patent-Laying Open No. 2000-90663).
In a conventional DRAM where a read column select line and a write column select line are driven by the same power supply voltage, when the read column select line and the write column select line are driven by the power supply voltage for the array, a bit line pair and the read column select line both connected to a read column select gate are driven by the power supply voltage for the array. Hence, when the power supply voltage for the array decreases and the power supply voltage for the peripheral circuitry increases, the speed that electric charge is drawn from the read data line is lowered. However, the delay amount of a pre-amp activation signal generated by the power supply voltage for the peripheral circuitry is small, and an erroneous operation can happen such as the activation of preamplifier while the potential difference between read data lines of a read data line pair is small, which means that the timing margin is not sufficient. However, if, as a solution, the delay amount of the pre-amp activation signal is increased, the operating frequency becomes lower.
In addition, when the read column select line and the write column select line are both driven by the power supply voltage for the peripheral circuitry, the write column select line and a write data line pair, both connected to a write column select gate, are driven by the power supply voltage for the peripheral circuitry. Hence, with the increase of the power supply voltage for the array and the decrease of the power supply voltage for the peripheral circuitry, data inversion cannot always be caused due to the low drivability of the write column select gate compared with the drivability of a P-channel MOS transistor of a sense amplifier, thus the operation margin is not sufficient.
Hence, in the conventional DRAM where the read column select line and the write column select line connected to the read column select gate and the write column select gate, respectively, are driven by the same power supply voltage, when one power supply voltage is low and another power supply voltage is high, the timing margin and the operation margin become extremely small, whereby the stable high-speed operation cannot be sufficiently achieved.